Timing Model

The timing model shown in the Timing Model Diagram is an expanded version of the one in  MPEG standard ISO/IEC 13818-1, Annex D.  

Data flows at a constant (or specified) rate at the input to the encoder (Point A in the diagram) then at a variable rate at the encoder output before the encoder buffer (Point B), then at a constant rate out of the encoder buffer (Point C), through the R.F. channel, and into the decoder buffer (point D), then a variable rate into the decoder (Point E), and then a constant (or specified) rate from the decoder (Point F).

The System Target Decoder is assumed to have zero delay in the decoder block, and the encoder and transmission path are also assumed to have zero delay, that is, the buffers represent the only system delay.  It will be seen that the zero-delay elements can also have a constant delay without disturbing the operation.

The decoder is synchronized with the encoder by time stamps, which are introduced in the following way. The encoder contains a master oscillator and counter, called the System Time Clock (STC).  (Refer to the Timing Model Diagram.)  The STC belongs to a particular program and is the master clock of the video and audio encoders for that program.  The case where there are multiple programs, each with its own STC, will be discussed in the section on Multiplexed Programs .  Note that it is valid within the MPEG standard for a particular program component to have no time stamps, but there is no way to synchronize an unstamped component with other components.

At the input of the encoder, Point A, the time of occurrence of an input video picture or audio block (and of the appearance of its coded version at the zero-delay encoder output) is noted by sampling the STC.  A constant quantity equal to the sum of encoder and decoder buffer delays is added, creating a Presentation Time Stamp (PTS), which is then inserted in the first of the packet(s) representing that picture or audio block, at Point B in the diagram.

Also entered into the bitstream under certain conditions is a Decode Time Stamp (DTS), which represents the time at which the data should be taken instantaneously from the decoder buffer and decoded.  Since the System Target Decoder delay is zero, the DTS and PTS are identical except in the case of picture reordering for B pictures.  The DTS is only used where it is needed because of reordering.  Whenever DTS is used, PTS is also coded.

PTS (or DTS) is entered in the bitstream at intervals not exceeding 700 mS.  ATSC further constrains PTS (or DTS) to be inserted at the beginning of each coded picture ( access unit ).

In addition, the output of the encoder buffer (Point C) is time stamped with System Time Clock (STC) values, called Program Clock Reference (PCR) if the stamp is at the transport packet level, or System Clock Reference (SCR) at the PES level.  PCR time stamps are required to occur at maximum 100mS intervals.   SCR time stamps are required to occur at maximum 700mS intervals.The  Program Clock Reference (PCR) and/or the System Clock Reference (SCR) are used to synchronize the decoder STC with the encoder STC. (See Decoder STC Synchronization )

The terminology may be a bit confusing at first:

In a Program Stream, the clock reference is called the System Clock Reference (SCR).  In a Transport Stream, the clock reference is called the Program Clock Reference (PCR).

All video and audio streams included in a program must get their time stamps from a common STC so that synchronization of the video and audio decoders with each other may be accomplished.  

The important characteristic of the system of PCR time stamps is that the data rate and packet rate on the channel (at the multiplexer output) may be completely asynchronous with the System Time Clock (STC), and the STC can still be synchronized at the decoder.  This also means that different programs that may have different STCs can be carried in a multiplex with other programs while allowing recovery of the STC for each program.

Operation depends on there being a constant net delay in the buffers and transmission channel for both the video and the audio.  This will naturally be the case if there is no underflow or overflow. Data is neither created nor destroyed by the transmission system, and the encoder input and decoder output run at equal and constant rates.  Thus there is also a fixed end-to-end delay (from input to the encoder to output from the decoder).

In MPEG systems where exact synchronization is not required, the decoder clock can be free running, with video frames repeated or skipped as necessary to prevent buffer underflow or overflow, respectively.  This type of decoder is not capable of lip sync and will not be considered further in this exposition.

Next: PCR - Program Clock Reference


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